1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of transistors having strained channel regions by using stress-inducing sources, such as embedded strain layers and the like, so as to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed close to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel, due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region is a dominant factor in determining the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length an important design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is the development of enhanced photolithography and etch strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for a new device generation. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions in order to provide low sheet and contact resistivity in combination with a desired channel controllability. In addition, the vertical location of the PN junctions with respect to the gate insulation layer also represents a critical design criterion in view of leakage current control, since reducing the channel length may usually also require reducing the depth of the drain and source regions with respect to the interface formed by the gate insulation layer and the channel region, thereby requiring sophisticated implantation techniques. According to other approaches, epitaxially grown regions are formed with a specified offset to the gate electrode, which are referred to as raised drain and source regions, providing increased conductivity of the raised drain and source regions, while at the same time maintaining a shallow PN junction with respect to the gate insulation layer.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques concerning the above-identified process steps, it has been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node, while avoiding or at least postponing many of the above process adaptations associated with device scaling. One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region increases the mobility of electrons, wherein, depending on the magnitude and direction of the tensile strain, an increase in mobility of 50% or more may be obtained, which, in turn, may directly translate into a corresponding increase in the conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
Consequently, it has been proposed to introduce, for instance, a silicon/germanium layer or a silicon/carbon layer in or below the channel region to create tensile or compressive stress that may result in a corresponding strain. Although the transistor performance may be considerably enhanced by the introduction of stress-creating layers in or below the channel region, significant efforts have to be made to implement the formation of corresponding stress layers into the conventional and well-approved MOS technique. For instance, additional epitaxial growth techniques have to be developed and implemented into the process flow for forming the germanium or carbon-containing stress layers at appropriate locations in or below the channel region. Hence, process complexity is significantly increased, thereby also increasing production costs and the potential for a reduction in production yield.
Thus, in other approaches, external stress created by, for instance, overlaying layers, spacer elements and the like, are used in an attempt to create a desired strain within the channel region. Although a promising approach, the process of creating the strain in the channel region by applying a specified external stress may depend on the efficiency of the stress transfer mechanism for the external stress provided by, for instance, contact layers, spacers and the like into the channel region to create the desired strain therein. Hence, although providing significant advantages in terms of process complexity over the above-discussed approach requiring additional stress layers within the channel region, the efficiency of the stress transfer mechanism may depend on the process and device specifics and may result in a reduced performance gain for one type of transistor.
In another approach, the hole mobility of PMOS transistors is enhanced by forming a strained silicon/germanium layer in the drain and source regions of the transistors, wherein the compressively strained drain and source regions create uniaxial strain in the adjacent silicon channel region. To this end, the drain and source regions of the PMOS transistors are selectively recessed, while the NMOS transistors are masked and subsequently the silicon/germanium layer is selectively formed in the PMOS transistor by epitaxial growth. Although this technique offers significant advantages in view of performance gain of the PMOS transistor and thus of the entire CMOS device, an appropriate design may have to be used that balances the difference in performance gain of the PMOS transistor and the NMOS transistor.
In still a further approach, a substantially amorphized region is formed adjacent to the gate electrode by ion implantation and the amorphized region is then re-crystallized in the presence of a stress layer formed above the transistor area, as will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically shows a semiconductor device 100 comprising a substrate 101, such as a silicon substrate having formed thereon a buried insulating layer 102, above which is formed a crystalline silicon layer 103. Moreover, the semiconductor device 100 comprises a gate electrode 104 formed above the silicon layer 103 and separated therefrom by a gate insulation layer 105. Moreover, a liner 106, for instance, comprised of silicon dioxide, is conformally formed on the gate electrode 104 and the silicon layer 103. The semiconductor device 100 is exposed to an ion implantation process 108 which may be designed such that a region 112 of the silicon layer 103 located adjacent to the gate electrode 104 is substantially amorphized. Furthermore, a doped region 107 may be formed within the layer 103 and may comprise any appropriate doping species that is required for the specific transistor to be formed by means of the gate electrode 104.
A typical process flow for forming the semiconductor device 100 may comprise the following processes. After forming or providing the substrate 101 having formed thereon the buried insulating layer 102 and the silicon layer 103, appropriate implantation sequences may be performed to establish a desired vertical dopant profile within the layer 103, which for convenience is not shown in FIG. 1a. Thereafter, any appropriate isolation structures (not shown), such as shallow trench isolations or the like may be formed. Next, an appropriate dielectric material may be formed by deposition and/or oxidation followed by the deposition of an appropriate gate electrode material, wherein both layers may then be patterned on the basis of sophisticated photolithography and etch techniques. Subsequently, the liner 106 may be formed on the basis of well-established plasma enhanced chemical vapor deposition (PECVD) techniques, wherein, depending on the process requirements and strategy, the liner 106 may act as an offset spacer for the formation of the doped region 107 on the basis of well-established implantation techniques. Furthermore, prior to or after the formation of the doped region 107, which may comprise a P-type dopant or an N-type dopant, depending on whether a P-channel transistor or an N-channel transistor is to be formed, an amorphization implantation process 108 may be performed. For this purpose, an appropriate dose and energy for an implant species under consideration may be selected on the basis of well-established recipes, thereby forming the substantially amorphized regions 112. For example, xenon, germanium and other heavy ions are suitable candidates for the amorphization implantation 108. Thereafter, a spacer layer may be formed above the semiconductor device 100 in such a way that the corresponding spacer layer may exhibit a specified type of intrinsic stress, such as tensile or compressive stress, wherein, after the deposition of the layer or after a subsequent patterning of the spacer layer into respective sidewall spacers on the basis of anisotropic etch techniques, an anneal process may be performed in order to re-crystallize the substantially amorphized regions 112.
FIG. 1b schematically shows the semiconductor device 100 after the completion of the above-described process sequence, in which a sidewall spacer 109 having a high intrinsic stress, in the present example indicated as a tensile stress, is formed on sidewalls of the gate electrode 104, while the substantially amorphized regions 112 are substantially re-crystallized and are now indicated as 112A. Due to the presence of the highly stressed spacer layer or the spacer 109, the re-crystallized regions 112A are re-grown in a strained state, thereby also creating a respective strain 110 in a channel region 115 located below the gate electrode 104. Thereafter, the semiconductor device 100 may be subjected to further manufacturing processes for providing a transistor element having the strained channel region 115.
FIG. 1c schematically shows the semiconductor device 100 with an additional spacer element 111 formed adjacent to the spacer 109 and with respective drain and source regions 113 formed within the silicon layer 103 and also partially within the strained re-crystallized region 112A. The device 100 may be formed in accordance with well-established processes, such as further implantation sequences, on the basis of the spacer element 111 in order to obtain the required dopant profile for the drain and source regions 113.
Consequently, an efficient technique for the creation of the strain 110 within the channel region 115 is provided which may lead to a significant enhancement in the charge carrier mobility and, thus, in the conductivity of the device 100. During the operation of the device 100, however, a significant increase in leakage current may be observed, which is believed to be caused by crystalline defects 114, which may also be referred to as “zipper defects,” and which may represent a source of reducing the minority charge carrier lifetime, thereby possibly significantly contributing to an increase of leakage current.
Although the approach described with respect to FIGS. 1a-1c provides the potential of a significant performance gain for N-channel transistors and P-channel transistors, there is still room for improvement, for instance in enhancing the strain transfer, reducing the leakage currents and the like.
In view of the situation described above, a need exists for an improved technique for the formation of transistor elements with a strained channel region, while avoiding or at least reducing the effects of one or more of the problems identified above.